Silicon Labs /EFR32MG21A010F1024IM32 /IADC0_S /SCANFIFOCFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCANFIFOCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RIGHT12)ALIGNMENT 0 (SHOWID)SHOWID 0 (VALID1)DVL0 (DISABLED)DMAWUFIFOSCAN

DMAWUFIFOSCAN=DISABLED, DVL=VALID1, ALIGNMENT=RIGHT12

Description

Scan FIFO Configuration

Fields

ALIGNMENT

Alignment

0 (RIGHT12): ID[7:0], SIGN_EXT, DATA[11:0]

3 (LEFT12): DATA[11:0], 000000000000, ID[7:0]

SHOWID

Show ID

DVL

Data Valid Level

0 (VALID1): When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA.

1 (VALID2): When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

2 (VALID3): When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

3 (VALID4): When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

DMAWUFIFOSCAN

Scan FIFO DMA Wakeup

0 (DISABLED): While in EM2 or EM3, the DMA controller will not be requested.

1 (ENABLED): While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).]

Links

()